| 摘要 |
PURPOSE:To prevent a horizontal AFC loop from being influenced by an equalizing pulse, by applying a synchronizing signal which has removed the equalizing pulse, to a phase comparator. CONSTITUTION:A differential positive polarity pulse of the composite synchronizing signal input (a) is applied to one input of the NAND circuit 7. A fly-back pulse (c) from the oscillating output circuit 4 is input to the other input of the NAND circuit 7, and negative logical product is taken. An output of the NAND circuit 7 is applied to the inverter 8 and the NAND circuit 10 through the clamp circuits (C1, D) and the low pass filter (R1, R2, C2). Accordingly, in a synchronizing status, a horizontal synchronizing signal of negative polarity from which an equalizing pulse has been removed appears in the output terminal of the NAND circuit 7. Resulting from the foregoing, an output of the NAND circuit 11 becomes a low level, and an output of the NAND circuit 12 becomes a high level. In consequence, a synchronizing signal from which an equalizing pulse has been removed is applied to the input of the phase comparator 3, and the AFC loop including an integrator 5 is operated stably. |
