| 摘要 |
PURPOSE:To unify a matrix circuit by using a temporary memory circuit, a differential circuit and an integrated circuit for the priority decision circuit and the buffer circuit. CONSTITUTION:When a priority decision signal is input to the input terminal A, an outut of the gate G1 is input to the priority decision circuit G3, and its output gives the information of the fact that the priority has been secured, to the buffer circuit G5, and at the same time it is fed back and sent out to the temporary memory circuit G11. The gate G1 is inhibited by an output of the circuit G11. At the same time as the foregoing, only that which has been varied through the differential circuit G7 is differentiated again as an inhibitive signal through the intersecting point connection P4 connected to the same output side as the intersecting point connection P3 of the matrix M2, and it is provided to an input of the memory circuit G12. The circuit G12 is stored temporarily by this input signal, and it is given to the gate G2 as an inhibitive information. After that, even if a priority decision signal is input to the input terminal C, the gate G2 remains closed and it is not input to the gate G4. |
