Microelectronic fabrication method minimizing threshold voltage variation.

摘要

A microelectronic fabrication process for minimizing the threshold voltage variation across the surface of a wafer of semiconductor material. The process precisely specifies the degenerate (or heavily doped) impurity profile distribution by using ion implantation so as to minimize the autodoping of adjacent gate regions immediately after the ion implantation step prior to gate oxidation, while maximizing the surface concentration of the dopant at the ultimate silicon surface to achieve appropriate surface sheet resistance and junction depth after all circuit fabrication steps have been completed.