| 摘要 |
<p>PURPOSE:To provide an asynchronous memory circuit with the speed-power product nearly equal to that of synchronous one by applying address signals to one-side inputs of exclusive-OR gates and then by supplying those signals to other-side inputs of the gates by delaying. CONSTITUTION:Address signals A0...An, applied to input terminals, are supplied to one-side inputs of exclusive-OR gates EX0...EXn and also supplied to other-side inputs of corresponding gates EX0...EXn via delay circuits D0...Dn. Then, outputs OS0...OSn of respective gates EX0...EXn are input to OR gate R, which outputs internal clock CE. Consequently, the asynchronous IC memory using the internal clock generated inside of it can be given the speed-power product nearly equal to that of synchronous one.</p> |
