| 摘要 |
<p>ENHANCEMENT-MODE FETS AND DEPLETION-MODE FETS WITH TWO LAYERS OF POLYCRYSTALLINE SILICON Enhancement-mode field-effect transistors (FETs) and depletion-mode FETs are provided on the same semiconductive substrate using five basic, lithographic, patterndelineating steps. The five lithographic masking steps delineate in order: (1) the field isolation regions; (2) the enhancement-mode FET gate electrodes; (3) the depletion-mode FET gate electrodes; (4) contact holes or vias to FET source and drain regions and to depletionmode FET gates; and (5) the high electrical conductivity metallic-type interconnection pattern. The low-concentration doping required to form the depletionmode channel regions is provided after the second but before the third pattern delineation step, while the highconcentration doping to form the source and drain regions is provided after the third pattern delineation step. In order to obtain the desired device structure, it is necessary to use two separately defined polycrystalline silicon regions for the gate electrodes of the enhancement-mode and depletionmode FETs. Using the five basic lithographic masking steps, FET integrated circuits can be fabricated that contain both enhancement-mode and depletion-mode FETs interconnected as desired.</p> |
