发明名称 Frame synchronizer having a write-inhibit circuit
摘要 A frame synchronizer for a television receiver in which the incoming television signal is digitized and stored in a memory, includes a circuit for generating a write-inhibit control signal for inhibiting the write-in of a digitized second television signal into the memory between the switchover from a first television signal to the second television signal and the beginning of a complete frame of the second television signal.
申请公布号 US4231063(A) 申请公布日期 1980.10.28
申请号 US19790039321 申请日期 1979.05.16
申请人 NIPPON ELECTRIC CO., LTD. 发明人 ITO, YUTAKA;INOUE, YUZO;SHIMIZU, TAKAO;INABA, MASAO;SUGIMOTO, ATSUMI;EMORI, TAKEO
分类号 H04N5/073;(IPC1-7):H04N5/04;H04N5/22;H04N9/46 主分类号 H04N5/073
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