| 摘要 |
PURPOSE:To attain the normal NAND action via the dual gate FET at a low signal level, by giving the drive to the level of the logic signal applied to the 2nd gate of the dual gate FET and with a shift toward the positive direction in comparison with the level of the signal to be applied to the 1st gate. CONSTITUTION:Dual gate FET41 is formed with use of n-type crystal layer 16 which is formed on high-resistance GaAs substrate 15, and active load 21 comprising the FET is connected to drain electrode 11. Then the power voltage is set to 6V, and the logic signals composed of the binary of 0V and -2V plus the binary of 0.5V and -1.5V are applied to the 1st and 2nd gates G1 and G2 each. In such way, the compensation is given to the autobias component and thus the potential of the 2nd gate is shifted toward the positive direction by the amount of that compensating potential. |
