| 摘要 |
PURPOSE:To reduce judgement errors by allowing a judgement feedback phase lock loop DFFLL controller to disregard signals detected within a fixed erasure zone. CONSTITUTION:A complex input signal is multiplied by a complex feedback signal by multiplying circuit 30, whose output has a specific constellation point detected by complex symbol detector 34. The input and output signals of detector 36 are compared to each other by modulation removal phase detector 36, which generates an error signal proportional to the difference between the input and output signals. Simultaneously, the output of multiplier 30 is supplied to erasure zone detector 42, which judges whether a complex input signal point is in the erasure zone. An error signal high in error possibility detected by detector 42 is prevented by switch 44 from being input to loop filter 38 and the other error signal is converted by filter 38 and exponential circuit 40 into a complex feedback signal, which is input to multiplying circuit 30. Consequently, judgement errors can be reduced. |
