| 摘要 |
PURPOSE:To shorten the time of data transmission by adding a control bit and inversion bit to data, exercising input-output control among processors before sending and by bringing error detection to effect at a reception side. CONSTITUTION:On ring transmission line L, stations STn, STn+1... are cascaded, and to respective stations, CPU1n, CPUn+1... are connected for input-output control over data among the stations. The format of the data consists of pieces of information HWH1 and HWH2, transmitted data (i), and block check character BCC. Inversion bits are added to respective bits of station addresses SAn+1 and SAn of a transmission destination and transmission origin, commands C1-C3, and data D constituting pieces of information HWH1 and HWH2 and the receiving station, when detecting an error by those pieces of information, sends an error message to the transmission origin to lessen the generation of the time over of the transmission origin, so that the shortening of the time of data transmission and the improvement of the utilization efficiency of the circuit will come into effect. |
