Boundary scheme for embedded poly-SiON CMOS or NVM in HKMG CMOS technology

摘要

The present disclosure relates to a structure and method for reducing CMP dishing in integrated circuits. In some embodiments, the structure has a semiconductor substrate with an embedded memory region and a periphery region. one or more dummy structures are formed between the memory region and the periphery region. Placement of the dummy structures between the embedded memory region and the periphery region causes the surface of a deposition layer therebetween to become more planar after being polished without resulting in a dishing effect. The reduced recess reduces metal residue formation and thus leakage and shorting of current due to metal residue. Further, less dishing will reduce the polysilicon loss of active devices. In some embodiments, one of the dummy structures is formed with an angled sidewall which eliminates the need for a boundary cut etch process.

主权项

1. An integrated circuit (IC), comprising:
a semiconductor substrate comprising a first region and a second region separated by a boundary region; a non-volatile memory (NVM) or a poly SiON (silicon oxy-nitride) CMOS device located over the first region; a periphery circuit disposed over the second region; one or more electrically inactive dummy structures laterally disposed between the NVM or the poly SiON CMOS device and the periphery circuit, wherein a bottom surface of the one or more electrically inactive dummy structures is disposed over a top surface of the semiconductor substrate; and a shallow trench isolation (STI) region comprising a first upper surface and a second upper surface that is recessed to a depth in comparison with the first upper surface to provide a recessed portion of the STI region, wherein the recessed portion of the STI region is laterally offset from the one or more electrically inactive dummy structures.