Memory refresh control apparatus.

摘要

Memory refresh control apparatus for a memory M has a refresh control circuit (RCON) which delivers n-bit (bits b1, b2... bn) refresh addresses and refresh clock signals (RC) to the memory M for refreshing 2<n> refresh clock signals RC are delivered over a given interval (a refresh interval) of time P.
<??>The memory has 2<n+N> addresses to be refreshed over the interval P. Clock divider circuit A provides N divided refresh clock signals for each refresh clock signal RC, and overheat bit generator A, supplied with the divided refresh clock signals, produces N-bit addresses in dependence upon a count of those signals. The n-bit and N-bit addresses are combined to produce (N+n)-bit addresses for refreshing the memory at the timings of the divided refresh clock signals.