发明名称 DRIVING CIRCUIT FOR CAPACITIVE LOAD
摘要 PURPOSE:To secure the flatness property for the capacitive load even to the low frequency input via the broad-duration pulse, by supplying repetivively the narrow- duration pulse to the DC cut-off coupling element. CONSTITUTION:The serial circuit of a pair of switching TRQ1 and Q2 plus Q3 and Q4 is connected to DC power source VS. And then capacitive load PDP such as the gas discharge element or the like is connected to the joint of TRQ1/Q2 and Q3/Q4, and pulse transformers T1-T4 functioning as the DC cut-off coupling elements are connected to the input side of the switching TR. When broad-duration pulses i1-i4 are supplied to load PDP, clock pulses i12 and i34 are applied to the pulse transformer via NAND gates G1-G4 in the form of a series of narrow-duration pulses and within the time corresponding to the pulse duration. As a result, the occurrence can be eliminated for the sag at the flat area when the broad-duration pulse is supplied.
申请公布号 JPS55130236(A) 申请公布日期 1980.10.08
申请号 JP19790038138 申请日期 1979.03.29
申请人 FUJITSU LTD 发明人 YAMAGUCHI HISASHI;KURAHASHI KEIZOU;TAKAHARA KAZUHIRO
分类号 H03K5/135;G09G3/20;G09G3/22;H03K17/60;H03K17/66 主分类号 H03K5/135
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