| 摘要 |
PURPOSE:To obtain a signal processor which generates assuredly the Q code through the simple process, by securing the modulo 2 addition for the contents of the sequential shift register and the input data and then repeating one shift. CONSTITUTION:When first data W1 is supplied to input IN, the data is supplied to sequential shift registers 101 and 104 via modulo 2 adder 100. After the supply of data W1, AND gate circuit 103 opens to receive supply of one unit of clock CK and then to carry out the operation of matrix T. After this, AND gate circuit 103 closes, and next data W2 receives the modulo 2 addition via adder 100 along with contents R of the shift register and with every sequential bit to be then supplied. Thus gate 103 opens to carry out matrix operation T. In such way, the input and the shift are repeated up to W6 in sequence, thus obtaining the Q code to contents R of the shift register. |
