| 摘要 |
PURPOSE:To improve the withstand voltage of an electrostatic induction type transistor by increasing the specific resistance of the surface of the region between a source region and a gate region higher than the channel region to the degree of the depth of the source. CONSTITUTION:An n<->-type layer 9 having a specific resistance of 10-20OMEGAcm is formed on the surface of a SIT of the conventional n-channel in thickness substantially equal to the thickness of an n<+>-type source 5. When it is excessively thick, the resistance to the source is increased, the specific resistance of the channel is increased to decrease the gm. When it is excessively thin, it largely affects the withstand voltage between the source and the gate. Since the layer 9 may be controlled with any impurity density by an ion implantation process after completing all the diffusions, it is very advantageous. In case of the p-channel SIT, similar configuration is employed. According to this configuration the depletion layer in the vicinity of the surface is readily expanded to become high withstand voltage to provide high power and high efficient SIT. |
