| 摘要 |
PURPOSE:To ensure the steady and assured mode setting by counting the output signals of the PLL circuit after the first index signal is detected and then carrying out the phase matching for the color switching signals via the count output. CONSTITUTION:The first index signal is detected at the horizontal scanning start end of picture tube 10. With this detection signal, the phase matching is given at PLL circuit 40 to the signal which receives the phase comparison with the index signal, and then circuit 40 is locked immediately. At the same time, output signal S0 of circuit 40 is counted after the first index signal is detected. With this count output, the phase matching is carried out at 1/3-divider 50 and against the color fluorescent substance stripe of the color switching signal. Accordingly, the rise or the fall of the output signal of circuit 40 is used for the timing of divider 50; and the other is used for the timing of the mode setting each. As a result, the steady and assured mode setting becomes possible. |
