A PLL synthesizer for a multi-channel civil band transceiver uses a D-flip-flop between a voltage controlled oscillator and a programmable divider which are parts of the loop. A reference signal is divided in a first divider to form a signal representing the frequency difference between adjacent transceiver channels which is applied to a phase comparator in the loop and the reference signal is frequency divided in a second divider to obtain a signal applied to the clock input of the D-flip-flop.
