| 摘要 |
PURPOSE:To ensure the smooth switching with no disturbance given to the memory, by giving the delay to plural units of new clocks which operate nonsynchronously to each other and are switched as the clock switching time along with the driving given to the memory by the minimum cycle time of the memory. CONSTITUTION:Clock(B), address(B), read/write(B), data(B) and others are connected to the line corresponding to unit(A) 1 from unit(B) 2 via gate 6 as well as delay circuits 51-54 each. Then the interruption signal is delayed through delay circuit 55 featuring the same delay time, and gate 6 is turned on by the delayed signal. At the same time, two signals of before and after the delay perform the switching with gate 7 turned off and through the OR circuit and the inverter. Thus gate 7 is turned off to give assurance to the precharge due to the final clock of before switching. As a result, the data breakdown or the like can be prevented within the memory. |
