发明名称 KEY DATA DELAY CIRCUIT FOR AUTOMATIC PERFORMANCE PIANO
摘要 PURPOSE:To ensure the collection of the high-quality data to the soft tape by leading the both output of the shift register which gives the 1-frame delay to the detection data of the live performance and the shift register which the delay of the same time to the output of the former shift register, to OR circuit. CONSTITUTION:The two circuits of the shift register consisting of 1-circuit 64 stage and others are connected in series to static register DC. And shift register SR1 which gives the delay to the key data for the 128-bit equal one frame is provided, along with shift register SR2 which gives the delay further one frame to one-frame delayed data. Then the simultaneous conditions is satisfied by OR circuit OR for both output data of SR1 and 2 to cover the signal lacking for one frame for the transmission to data editing part DM. The delay time of several tens milli-second can be ignored at the detouch time in the case of the piano. Accordingly, the high-quality data can be collected to the soft tape of the piano, at the same time, increasing the effect of the live performance.
申请公布号 JPS55125591(A) 申请公布日期 1980.09.27
申请号 JP19790031560 申请日期 1979.03.16
申请人 NIPPON MARANTZ 发明人 UEDA MASATO;KUWATANI YOSHIO
分类号 G11B31/02;G10H1/00 主分类号 G11B31/02
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