| 摘要 |
An arithmetic logic unit bit-slice implemented as an integrated circuit is able to perform iterative algorithms such as multiply and divide, using control logic which is also part of the integrated circuit to cause the selected algorithm to be performed. A plurality of the arithmetic logic unit bit-slices may be concatenated to provide the word size desired. The bit-slices are electrically identified as the most significant, least significant, and middle digits, such identification being provided to the control logic so that the control logic is identical on each bit-slice irresepective of its position within a word to enable the control logic to cause performance of the algorithms for any desired word length.
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