| 摘要 |
PURPOSE:To secure the synchronism by giving the inversion to the 1/2 division clock via the exclusive OR circuit in case no synchronism is detected for the output of the synchronous detection circuit, thus decreasing the number of the circuit elements rquired. CONSTITUTION:The bit clock supplied from terminal B receives the 1/2 division at FF1 to be used for the input of one side EXOR circuit 14, and the clock of the same or opposite phase C or C' is delivered according to 0 and 1 of the input of the other side each. The synchronous pattern given from terminal A is memorized in shift register 3 with every 1 bit and via clock C; while the synchronous pattern which is delayed by 1 bit at FF2 is memorized is shift register 4 with every 1 bit respectively. The output of both registers 3 and 4 are supplied to coincidence detection circuit 5 for the decision of coincidence with the frame synchronous pattern. With detection of this coincidence, the output of FF10 features 1. And the output of FF13 is inverted to become 1 if no coincidence is detected within the fixed time determined by monostable multivibrator 11. At the same time, the phase of the clock features C' to repeat the action mentioned above. |
