发明名称 SUBTRACTION CIRCUIT IN ELECTRIC CHARGE TRANSFER DEVICE
摘要 A circuit is disclosed for obtaining a quantity of electrical charge carriers equal to and representative of the algebraic difference between the values of two original quantities of electrical charge carriers. The circuit includes two charge coupled device input shift registers. Each of the two shift registers incorporates at least three potential well electrodes and interposed transfer electrodes such that charge packets can be shifted from well to well. One potential well in each of the two shift registers is operated in a floating gate electrode mode, and the two potential wells are connected at a common node which services as the input to a third or output charge coupled device shift register. The two original quantities of electrical charge carriers are represented respectively in each of the two input shift registers by a pair of spatially separated charge packets which when sensed by sequencing them into and out of the potential well under the floating gate electrode provide the algebraic value of the associated quantity of electrical charge carriers. By representing each original charge quantity by two spatially separated pairs of charge packets, positive and negative algebraic values may be representing even though all the charge quantities are made up of charge carriers of the same polarity. Combining the two floating gate electrodes at the common node rectifying input to the third or output shift register produces an algebraic value in the output shift register which represents the difference between the original charge packets.
申请公布号 JPS55121575(A) 申请公布日期 1980.09.18
申请号 JP19800003708 申请日期 1980.01.18
申请人 IBM 发明人 NEISAN POOTAA EDOWAAZU;JIEEMUZU MERIRU HOWAITO
分类号 G11C27/04;G06G7/14;H01L21/339;H01L29/76;H01L29/762;H01L29/768;H01L29/772;H03K23/40;H03K23/80;H03K25/00 主分类号 G11C27/04
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