| 摘要 |
Apparatus for providing a closed loop data path within a memory module to enable a central processing unit (CPU) to test the error correction circuitry of the memory module under software control without the necessity of accessing the memory arrays within the memory module. The memory module has error correction circuitry providing single bit correction/double bit detection. The error correction circuitry generates an error code which is appended to each data word upon being written into the memory array of the memory module. The error correction circuitry uses the error code to detect and correct errors in each data word read from the memory array of the memory module. A status register within the memory module stores control and status information for communication between the central processing unit and the memory module. Two bit positions of the status register are dedicated to closed loop error correct. If both bit positions contain binary zeroes, the memory module operates normally. If one of the bit positions contains a binary one, a read or write command to the memory module causes a read from or write into temporary storage of the error code within the error correction circuitry. If the other bit position contains a binary one, a read or write command to the memory module causes a read from or write into temporary storage of the memory module rather than a read into or write from the memory array of the memory module. Using the capability to read from and write into the temporary storage of the memory module, a CPU may directly test the error correction circuitry under software control without reading from and writing into the memory array of the memory module. |
