发明名称 SELF-RUNNING FREQUENCY STABILITY COMPENSATION TYPE PLL CIRCUIT
摘要 PURPOSE:To compensate the stability of self-running frequency without increasing the circuit scale by adopting the constitution such that a selector used to output a reference input signal or the like from a reference oscillator selectively and backing up the state at input signal interruption. CONSTITUTION:If a write clock WCLK is interrupted, a selector 11 is thrown in a way that a reference input signal from a reference oscillator 12 is outputted to a set terminal of an RS FF6. The input signal acts like an input signal of a PLL circuit, the phase of the input signal and the phase of the readout clock as the output signal of the PLL circuit are compared and the result is given to an IPF (low pass filter) 7, integrated and its output controls the self- running frequency of the output of a voltage controlled oscillator VCO 8. Thus, the reference oscillator 12 with small size and high performance is used to back up the state at write clock WCLK interruption thereby compensating the stability of the self-running frequency.
申请公布号 JPH01180151(A) 申请公布日期 1989.07.18
申请号 JP19880004019 申请日期 1988.01.12
申请人 FUJITSU LTD 发明人 ISHIZAKI TOSHIHARU
分类号 H03L7/14;H04J3/07;H04L7/00;H04L7/02;H04L7/033 主分类号 H03L7/14
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