发明名称 ARITHMETIC SYSTEM FOR FLOATING DECIMAL POINT
摘要 PURPOSE:To avoid the disturbance of pipeline processing by finishing the process of >=3 digits earlier by one cycle in case of the normalization quantity of >=3 digits and then holding a stage preceding a normalization stage in case of the normalization quantity of >=3 digits respectively. CONSTITUTION:An arithmetic system for floating points consists of a 1st normalization shifter means 71 which shifts all digits of an intermediate solution received from an addition/subtraction stage 5, a means 6 which holds data normalized by the means 71 via a normalization stage, a 2nd normalization shifter means 72 which shifts <=21 digits of the intermediate solution, a means 8 which sends the data normalized by the means 72 to the next stage, and a signal production means 1 which produces the signal to select the optimum one of both means 71 and 72 in the timing preceding the stage 5 and based on the data undergone no digit matching. Then a normalizing action is carried out at the normalization stage in accordance with the instruction of the signal produced by the means 1. In such a way, the disturbance of pipeline processing can be avoided.
申请公布号 JPH01180628(A) 申请公布日期 1989.07.18
申请号 JP19880005183 申请日期 1988.01.13
申请人 NEC CORP 发明人 ASANO SADAJI
分类号 G06F7/00;G06F7/76 主分类号 G06F7/00
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