| 摘要 |
An input circuit for use in the selection of one of n x m inputs signified by the closure of one of n x x m switch units. Each switch unit is a single pole switch connected between one of a first set of n terminals to which a first potential is applied and one of a second set of m terminals to which a second, different potential is applied. A circuit is provided for detecting the flow of current upon closure of a switch and for applying a potential to one of a third set of n terminals and one of a fourth set of m terminals dependent on the switch closed. Said circuit may comprise CMOS devices, allowing the input circuit to exhibit substantially zero quiescent power consumption.
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