发明名称 |
METHOD AND MAGISTRAL REGISTERED DEVICE FOR REALISING OF AUTOMATS- SEQUENCE TYPE |
摘要 |
<p>A register circuit for processing information in accordance with a given instruction set or set of transformation comprises N registers each having an input and an output and provided in a sequence R1, R2, R3, . . . RN, each register having n digits where N and n are integers. The output of the first register R1 is connected to a first bus while its input is connected to a second bus. All of the other registers R2, R3, . . . RN have their inputs connected to the first bus and their outputs to the second bus by respective strobe circuits. The strobe circuits of each of the buses R3 . . . RN are connected to respective control inputs a3 . . . aN. Additional control inputs a1 and a2 are connected to an OR-gate whose output is applied to the input strobe circuit of register R2 while the input a2 is also applied directly to the output strobe circuit of register R 2. This allows transfer of the contents of the first register to the second upon the application of a signal to the input a1 and parallel transfer between all the registers by the appropriate control inputs.</p> |
申请公布号 |
BG29106(A1) |
申请公布日期 |
1980.09.15 |
申请号 |
BG19780041322 |
申请日期 |
1978.11.08 |
申请人 |
DAKOVSKI,LJUDMIL G.;KASABOV,NIKOLA K. |
发明人 |
DAKOVSKI,LJUDMIL G.;KASABOV,NIKOLA K. |
分类号 |
G06F7/00;G05B15/02;G05B19/07;G06F9/22;G06F9/315;(IPC1-7):G06F7/00;H03K19/00 |
主分类号 |
G06F7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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