| 摘要 |
PURPOSE:To decrease the hardware without increasing the conversion processing- time, without correction of the decimal digit when the most significant bit of the shifter is ''1'', and by decimal correction by reducing ''6'' from the decimal digit in other cases. CONSTITUTION:In the system converting the binary number B into binary decimal number according to equation I, the two input decimal adder 13 has binary coded decimal number to one input A0 and +6 is inputted to another input A1 in response to each decimal number. Further, the register 15 stores the binary coded decimal number output of the adder 13, the register 16 stores the binary number to perform binary-decimal conversion, the shifters 17, 18 shift left by one bit the content of the registers 15, 16, and it is inputted to A0 of the adder 13. When the most significant bit of the decimal digit of the shifter 17 is ''1'' or in case of binary addition, if carry is produced from the most significant bit of the decimal digit, the adder 13 does not perform the correction 14 of the decimal digit and if any of them is not established, ''6'' is subtracted from the decimal digit for decimal correction 14. Thus, without increasing the conversion processing time, the amount of hardware can be reduced. |
