| 摘要 |
<p>PURPOSE:To make unnecessary the alteration of existing hardware and to assure the write-in time to erasable ROM, by informing the end of memory access from the start of monitor to the detection of malfunction, to the CPU monitoring memory cycle. CONSTITUTION:In the system assuring the write-in time to erasable ROMs2, 3 given to the information processor, the write-in timing circuit 13 does not receive the memory access request from CPU1 during write-in operation and receives the memory access request not during write-in operation. Further, the circuit 13 transfers the memory busy signal to the data line 14, and produces the state through the data line 6 as if there were memory access request by the direct memory access to CPU1 during the write-in operation. Further, the memory access end signal is delivered to CPU1 monitoring the memory cycle through the data line 6 from the circuit 13,- while the monitor start to malfunction detection. Thus, the write-in time to erasable ROMs2, 3 can be assured.</p> |
