发明名称 |
LOGIC LEVEL TRANSLATOR OR CML-T2L USED IN ALL CML TECHNOLOY |
摘要 |
<p>LOGIC LEVEL TRANSLATOR A logic level translator utilizes a TTL logic gate, a current switch, and a clamp circuit to convert CML level binary signals into TTL level binary signals. The translator provides isolation between the TTL ground and the CML ground in order to reduce noise in the CML portion of the circuit. The clamp circuit prevents a switching transistor in the current switch from reaching saturation, therby increasing the speed of operation of the translator. A portion of the current switch provides a quick pulldown of a switching transistor in the TTL circuit to reduce noise in the TTL circuit.</p> |
申请公布号 |
CA1085515(A) |
申请公布日期 |
1980.09.09 |
申请号 |
CA19760246167 |
申请日期 |
1976.02.20 |
申请人 |
HONEYWELL INFORMATION SYSTEMS INC. |
发明人 |
FETT, DARRELL L.;BIRD, DAVID A.;RAUSER, JERRY L. |
分类号 |
H03K19/018;(IPC1-7):06F5/00 |
主分类号 |
H03K19/018 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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