发明名称 SEQUENTIAL CONTROLLER
摘要 PURPOSE:To make it possible to constitute a controller at low cost while reducing memory capacity for a diagnostic program by storing the contents of a program counter when a combination inhibition condition is met and then by displaying input and output signals. CONSTITUTION:This unit consists of input part 67 (input lines are denoted as 13 and 14), output part 69 (putput lines are denoted as 15), oscillator 60 which generates pulses advancing program counter 61, memory 64 (stored with a program describing normal control functions and that inhibiting the combination of logical conditions) whose addresses are driven by counter 61, 1st coincidence circuit 72 which outputs 73 a coincidence signal when the address part of an instruction outputted from memory 64 agrees with an address set by digital switch 71, and 2nd coincidence detection circuit 78 which generates coincidence output 79 when the content of counter 61 agrees with the output of preset counter 76 and then holds 80 the instruction while displaying 90 the address part of the instruction.
申请公布号 JPS55116104(A) 申请公布日期 1980.09.06
申请号 JP19790023759 申请日期 1979.02.28
申请人 发明人
分类号 G06F11/22;G05B15/02;G05B19/02;G05B23/02 主分类号 G06F11/22
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