| 摘要 |
PURPOSE:To increase the yield rate at the final test process, by decreasing the measuring time and increasing the content of test, through the combination of the application of input frequency within specified time and the drive of a signal pulse. CONSTITUTION:When the set reset state of the D type flip flop 3 is released, the frequency dividing circuit 2 starts the operation, and the final stage comes from L to H, the gate 6 turns on. At the gate-on time only during a half cycle, the input frequency in f hertz is fed to DUT from the crystal oscillation circuit 4 and a half cycle only is advanced to discriminate the frequency divided output of DUT. Next, to advance the state of DUT by further a half cycle, the frequency division circuit 2 is operated, f hertz is fed to DUT by a half cycle to discriminate the state of DUT. Further, when a single pulse is fed to DUT from the single pulse driver 7, it is discriminated for one bit advancement from the initial state. |
