| 摘要 |
PURPOSE:To make it possible to observe a system state statically by stopping system clocks during access, by providing a memory circuit stored with state of access to a dynamic memory. CONSTITUTION:The oscillation clock of oscillator OSL is divided into unconditional clock CK and system clock SCK and register REG memorizes the content of refresh counter CNT at the point in time when a stop request arrives. Once the stop request arrives during access to D memory MEM, clock SCK stops immediately. Therefore, the state of the system during access can statically be observed. On arrival of a start request, the content of register REG is read out and when the state before the access stop is set, clock SCK is generated again by the coincidence output of comparator COMP, thereby restarting access to a dynamic memory. |
