发明名称 CLOCK UNIT FOR INFORMATION PROCESSING SYSTEM
摘要 <p>PURPOSE:To enable the clock operation by the second unit even if the first unit is in failure, by incorporating the real time timer to each unit, in the information processing system consisting of the first unit and a plurality of the second units. CONSTITUTION:In the system consisting of the centralized monitor unit CSC3 and a plurality of CPU4, each unit incorporates the real timers 2, 1 respectively. The timer 2 counts the real time standard value of the timer 1 via the clock set instruction line 18 and the timer value supply line 15. If the CSC3 is normal, the signal of the clock effective display line 17 is 1, the selection circuit 11 selects the clock of the clock generation circuit 5, and if the CSC3 is in failure, the signal on the line 17 is 0 with the failure detection circuit 6, and the circuit 11 selects the clock of the clock generating circuit 12. The clock count clock from the circuit 11 is fed to the timer 1 via the timer control circuit 10.</p>
申请公布号 JPS55112621(A) 申请公布日期 1980.08.30
申请号 JP19790018341 申请日期 1979.02.21
申请人 HITACHI LTD;NIPPON TELEGRAPH & TELEPHONE;NIPPON ELECTRIC CO;FUJITSU LTD 发明人 MINAMI HIDEKAZU;HIRANO MASANORI;YASUMI NAOAKI;NARITA YUUICHI
分类号 G06F1/14;G04G99/00;G06F1/00 主分类号 G06F1/14
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