| 摘要 |
PURPOSE:To obtain a safe clocked gate logic circuit which is capable of a high- speed operation by setting the minimum potential at the absolute value of the clock which controls the transfer-use FET higher than the absolute value of the FET's threshold voltage. CONSTITUTION:Control signal phiS is connected to the gate electrode of N-channel transfer gate MS and then turned into output Out1 via the joint between pre-charging P-channel FETMp and FETMS. The pre-charging is given with control signal phiL set to the O-level, and then the pre-charging is cut off at 30mu sec. which still features a high voltage rising factor. The charge division is caused for logic-use N- channel FETSM1-M128 as soon as signal phiL features 1-level, and thus the balanced potential is secured to all nodes of 128 steps. The level of signal phiS is lowered after the sampling, and thus FETMS is pinched off. And Out1 keeps assuredly the 1-level of the charging time. |
