| 摘要 |
PURPOSE:To reduce the number of elements per a memory cell, by connecting two MONOS transistors in series with a single intermediate IGFET between two nodes of a bistable circuit made of IGFETs. CONSTITUTION:The bistable circuit of a conventional static memory cell is made of enhancement-type IGFETs Q11, Q12 and depression-type IGFETs Q13, Q14. MNOS transistors MT11, MT12 are connected in series with an intermediate enhancement- type IFGET Q15 between the connection node N11 of the drain of the IGFET Q11 with the source of the IGFET Q13 and that N12 of the drain of the IGFET Q12 with the source of the IGFET Q14. The gates of the MNOS transistors MT11, MT12 are coupled to a control signal line MG. The gate of the IGFET Q15 is coupled to an inverted signal line MG of inverse phase to the signal line MG. Information to the bistable circuit can be stored in the MNOS transistors or the stored information can be read, by applying a signal voltage. According to this constitution, the number of elements is reduced. |
