发明名称 |
Combined timekeeper and calculator with low power consumption features |
摘要 |
A combined timekeeper and calculator implemented on an LSI semiconductor chip includes a generator stage for generating basic clock signals and system clock signals which are obtainable by modifying the basic clock signals, and a processor stage responsive to the supply of the system clock signals for performing the operations required for the timekeeper mode and calculator mode. The basic clock signals also are modified to create second signals useful in the timekeeper mode. The generator to supply the processor unit with the system clock signals while the second signal is being generated. Upon completing the operations by the processor unit, a clock control circuit prevents the processor unit from being supplied with the system clock signals.
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申请公布号 |
US4218876(A) |
申请公布日期 |
1980.08.26 |
申请号 |
US19770854214 |
申请日期 |
1977.11.23 |
申请人 |
SHARP K K |
发明人 |
HASHIMOTO, SHINTAROU;NAKAGAWA, HIROHIDE;NISHIMURA, TOSHIO |
分类号 |
G04G9/00;G04G99/00;G06F1/04;G06F1/32;G06F15/02;H02J1/00;(IPC1-7):G06F1/00;G04C23/00 |
主分类号 |
G04G9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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