Controllable capacitive circuit with large range of variations - has FET with controllable ohmic resistor between source and drain electrodes to form variable input capacitance

摘要

The circuit simulates an input capacitance whose value is a variable multiple of a capacity incorporated between the gate and source electrodes of a used f.e.t. The capacitor (C) is incorporated between a main electrode (D) (drain) and a control electrode (G1). Between the transistor (T1) source (S) and drain electrode (D) is incorporated a controllable ohmig resistor (R). Thus between the gate electrode and the source electrode is obtained an input capacity (Cei), the varying with the value of the controllable resistor. The transistor is pref. of the depletion type. The resistor may be formed by a second f.e.t, both transistors being integrated in a common semiconductor substrate. The capacity between the gate and drain electrodes may be also variable.