发明名称 PARALLEL PROCESSOR
摘要 PURPOSE:To reduce the idle time of a receiving processor by transmitting data to be transmitted to another processor to an address of a local memory in a transferred processor which is formed from a main identifier and a sub- identifier. CONSTITUTION:The identifier of data to be transmitted is constituted of the main identifier MK expressing a data group including the data and the sub- identifier SK for identifying the data from other data in its data station and the address of a storing local memory 3 in a transferred processor element (PE) based on the main identifier MK and the sub-identifier SK is generated. When the receiving processor executes processing forming an exchange rule, data necessary for the processing are extracted together with the sub-identifier SK successively from data arriving at the local memory by forming an address by means of the main identifier MK. Consequently, the idle time of the receiving processor can be minimized.
申请公布号 JPH01194056(A) 申请公布日期 1989.08.04
申请号 JP19880017073 申请日期 1988.01.29
申请人 HITACHI LTD 发明人 TANAKA TERUO;HAMANAKA NAOKI
分类号 G06F15/173;G06F15/16 主分类号 G06F15/173
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