| 摘要 |
PURPOSE:To ensure the accurate detection for the state of error by giving the correction and the polarity inversion to the 1-bit error, if detected, and then having a comparison between the data which generated the redundant bit and the preceding data which gave the polarity inversion. CONSTITUTION:The data supplied to SEC-DED code generation circuit 2 is supplied to data register 11 after the polarity inversion given through polarity inverter 9 in case the 1-bit error is detected by SEC-DED circuit 6 and via the redundant bit added by circuit 2. This data is furthermore supplied to circuit 2 in the form of retrial writing data 12. Circuit 2 adds again the redundant bit corresponding to the data for writing. And this output 3 is written into memory device 4 and then read out. This reading code 5 receives the detection of the 1-bit error through circuit 6. After this, reading data 7 is supplied to comparator 23 to be compared with data 12. When the coincidence is obtained through the comparison, only 1-bit error exists. While in case no coincidence is obtained, the correction is given to the 3-bit error. And the correction of the error is informed to outside. |
