Speed regulation of D.C. motor using counter

摘要

A semiconductor switch connected in the motor current path is controlled by a clocked flip-flop having a switch-ON and a switch-OFF state, capable of changing states only in response to a clock pulse. RPM is selected by establishing the initial count on a downwards counter having a carryover output at which a carryover signal appears when zero count is reached. A first higher-frequency pulse train is counted by the counter. A second lower-frequency train of set pulses has a repetition frequency dependent upon motor speed. The leading end of each set pulse starts the counter counting. An unclocked flip-flop responds to the carryover signal by assuming a motor-speed-too-low state. The clocked flip-flop when clocked responds to the state of the unclocked flip-flop. The trailing flank of the set pulse clocks the clocked flip-flop so that the latter can respond to the state of the unclocked flip-flop and slightly thereafter sets the unclocked flip-flop to the motor-speed-too-high state. Thus, at the time when the clocked flip-flop responds to state of the unclocked flip-flop, the latter is in the speed-too-low state only if the carryover signal was produced before the trailing end of the set pulse.