Detector circuitry

摘要

A low power high sensitivity detector having two pairs of MOS cross coupled transistors, voltage equalization circuitry, and a single input, with no external reference, forms the basic configuration of a detector-level shifter circuit which is compatible with today's single chip large capacity memories. The lengths of the channels of one of the pairs of cross coupled transistors are designed to be longer than the other pair. This provides a built-in imbalance which provides good tolerance to transistor parameter variation due to semiconductor processing variations.