| 摘要 |
PURPOSE:To cause an output load to be seen small according to output rise by using an insulating gate-type FET to control charging and discharging of required nodes in the inverter which converts the level of a prescribed external clock. CONSTITUTION:The level of the clock of a transistor logical level applied from the external to MOSFETQ3 of an insulating gate-type FET is converted to the level of clock phiS of the MOS transistor from node 2 connected to bootstrap capacity C1F between MOSFETQ2, which has the source connected to power source VDD, and MOSFETQ4, which has the gate connected to node 4 between MOSFETQ4 and Q6. The gate of MOSFETQ6 is connected to MOSFETQ7 and Q8 through node 5 similarly, and node 5 rises according as conversion clock phiS rises, and node 4 is discharged through FETQ6, and FETQ4 becomes almost non-conductive. Consequently, the load capacity is seen small from node 2, so that the rise speed of conversion clock phiS after that can be enhanced. |
