JK flip=flop register of current flow logic type - has edge-triggered operation with function checking independently of operation

摘要

An edge controlled data register based on J-K musker slave flip-flops is developed in integrated circuit form as part of a current flow logic family. The register is designed with the facility for synchronous resetting and also for 5 bit serial data entry. The circuit operates in a negative logic mode. The master-slave operates to effect transfer into the master stage when the clock goes high. Transfer into the slave stage occurs when the clock goes low. The complete J-K flip-flop register consists of five identical stages with one stage having an input gate controlled by a signal from a logic stage coupled to the final stage. Control of the master-slave J-K flip-flops depend upon control signals generated by a control and timing circuit.