| 摘要 |
PURPOSE:To improve the linearity of output performance and to avoid discontinuity, by outputting the potential of the output transistor according to the leading phase pulse width and lowering the potential according to the leading phase pulse width with the capacitor. CONSTITUTION:The reference frequency signal fR is given to the CP terminal of FF1 as the clock signal, and the variable frequency signal fs is given to the CP terminal of FF2. The phase of the both signal is compared, and when the phase of the signal fs is advanced than that of the signal fR, the capacitor C1 produces the potential in proportion to the phase difference. The transistor T4 outputs the potential according to the leading phase pulse width from the emitter and ground potential is given to the transistor T5 via the resistor R2 selectively with the signal in synchronizing with the signal fR from the emitter, and the potential according to the leading phase pulse width is lowered with the capacitor C2. Thus, the linearity of the output performance corresponding to the phase difference can be improved and the occurrence of the discontinuous points can be avoided. |
