| 摘要 |
PURPOSE:To secure application of the trigger to the time-series data pattern by installing the prescribed shift circuit to the logic analyzer. CONSTITUTION:The logic equalizer of, for example, 8 channels consists of input comparator COMP, sequential access memory SAM, threshold setting circuit THRH, word recognizer WRG, display unit DRY and others. Then shift circuit STC comprising cascade-connected FF302-309 plus inverter 318 is connected between COM and WRG. In such constitution, the value of input data 301 is transferred in sequence to FF309 from FF302 in synchronization with block signal 105, and at the same time output 310-317 are generated from each FF. These output are then supplied to WRG in order to obtain trigger signal 106 to the time-series data. |
