| 摘要 |
A method and system for the implementation of binary multiplication of a number by a sum of two numbers, applicable in the computer systems, particularly in the specialized processors for numerical computations. In the method according to the invention the multiplier, as expressed by two numbers-summands represented in a binary number system, is transformed parallelly into a positional number system with digits from -2g-1 to +2g-1, where "g" is the number of binary positions of multiplier. These two numbers correspond to one partial product-summand of the result. The multiplying system contains registers of multiplier summands, a register of the multiplicand, a system converting the multiplier summands, the system preparing the partial products and the system summing them. Signals are generated by the converting system and represent digits from -2g-1 to +2g-1 depending upon signals coming from at most three positon groups of each of registers of multiplier summands and, possibly also, upon signals coming from their sign positions.
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