Identification word generator - receives serial data from bus connecting CPU and peripherals and initiates reply signal

摘要

The data receiver receives data from a serial bus connecting a central processor to peripheral devices. For each peripheral device, the receiver contains a circuit producing pulses whose number corresponds to the total max. number of binary states supplied by the different peripheral devices. A shift register is connected via a logical inverter to the output of the circuit and one or more of its stages are connected to points in a memory serving the peripheral device concerned: the remaining stages are all connected to an inactive logic level. An AND-gate is connected by one input to the output of the circuit and by its other input to the output of the last stage in the register. The gate's output is connected to the tarnsmitter.