发明名称 BINARY ARITHMETIC CIRCUIT
摘要 PURPOSE:To improve processing speeds of absolute-value arithmetic, multiplication and division by making use of the uppermost digit of a data register, the lowermost digit of a multiplier register and the content of a carry output memory unit for a single microinstruction as an arithmetic basic step. CONSTITUTION:Under the control of logic circuit 36, the contents of 1st to 3rd registers R29, R30 and R31 are selected by selectors 32 and 33 by a mu-instruction from microinstruction memory unit 7 and are inputted to binary parallel adder 5 and the arithmetic result of adder 5 is outputted. For absolute-value addition, the contents or inversion values of R29 and R30 or ''0'' are selected by selectors 32 and 33 corresponding to the uppermost-digit values of R29 and R30. For multiplication, a multiplicand and multiplier are inputted to R29 and 3rd 31 respectively and initial value ''0'' is to R30. Corresponding to the lowermost-digit value of R31, addition results of respective digits between the multiplier and multiplicand are outputted and shifters 34 and 35 are brought under control to shift the contents of R30 and R31 as many times as the number of digits. For division, a divisor is inputted to R29, and dividends with digits twice are to R30 and R31 to attain substraction of each digit and control over shifters 34 and 35 corresponding to the contents of a carry output memory unit.
申请公布号 JPS5595148(A) 申请公布日期 1980.07.19
申请号 JP19790002106 申请日期 1979.01.10
申请人 HITACHI LTD 发明人 NISHIDA TAKEHIKO;FUKAZAWA SHIGERU
分类号 G06F7/505;G06F7/00;G06F7/50;G06F7/52;G06F7/53;G06F7/535;G06F7/537 主分类号 G06F7/505
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