发明名称 OUTPUT BUFFER CIRCUIT FOR PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To discharge the charge stored in the wiring capacity to reduce the readout time, by providing the constant current circuit with the output gate of PLA (Programmable Logic Array). CONSTITUTION:Between the output wiring l from the OR logic matrix array OR of the output buffer circuit BUF to the output gate OG and the ground GND, the constant current circuit consisting of the npn transistor Trb is connected in series with the discharge resistor R1. Since the time when the output of the array OR changes from H to L is the time to discharge the wiring capacitor C with the constant current i, the readout time can be reduced by several tens of % with suitable set of the current i.
申请公布号 JPS5593323(A) 申请公布日期 1980.07.15
申请号 JP19790002824 申请日期 1979.01.09
申请人 FUJITSU LTD 发明人 WASHIMI HIDEJI;KOMON MASAYUKI
分类号 H03K19/018;H03K19/177 主分类号 H03K19/018
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