| 摘要 |
PURPOSE:To avoid to reduce the effective capacity of transmission, by performing recognition of multi-frame section through the use of error judgement result of reception message, after the establishment of synchronism at the reception side. CONSTITUTION:The time sharing multiplex transmission line Hs is connected to the digital interface DTL, and the information pulse train reproduced is delivered to the time sharing exchanger switch frame TD-SWF and the control signal separation circuit CSEP via the signal line S1. The data message and error detection code separated in the separation circuit CSEP are delivered to the shift register SR in 40 bits sequentially via the signal line S2. The output of the error detection circuit FDE is inputted to the control processor CCP and the data message if judged as error presence, is abolished and if the judgement of error presence is continued, the shift register transfer pulse is delayed by one frame via the signal line S5 to take synchronism. |
